This disclosure relates to the field of static random access memories and similar circuits that maintain stored logic levels while power is applied, in particular with provisions to reduce power consumption when in an inactive or “sleep” mode. Bit lines are biased in sleep mode according to several embodiments, so as to facilitate switching into a standby mode for read or write operations, without an undue inrush of current to power up.
So long as power is applied to a volatile memory bit cell, the logic level of the bit cell is stable. Typically, two cross-coupled inverters hold one another in a present logic state that can be read out using a sense amplifier. The inverters can be forced by a write driver to switch to an opposite logic state, and then remain stable in that logic state. A sense amplifier and a driver are provided at each bit position in a bit cell array having plural word lines. For example, an array might have 256 bit positions and 256 word lines, or some other number. One word line is selected at a time by asserting a word line signal at all the bit cells along the associated word line, for read or write operations determined by logic values applied to or read from the bit lines.
The inverters can be isolated from the addressing lines by passing gate transistors. In a six transistor (6T) bit cell configuration, for example, the nodes at which two inverters are cross coupled (connected input-to-output) are isolated from two complementary bit lines BL, BLB by the source/drain channel of two passing gate transistors, each typically an NMOS field effect transistor (FET). When the associated word line signal WL is asserted at the gate of the passing gate FETs, the inverter nodes are coupled to the bit lines.
The inputs and outputs of the cross coupled inverters, which are the bit cell nodes, are not actively coupled externally until the bit cell is addressed by the word line and bit line signals that cross at the bit cell. The value stored in the bit cell is thereby protected while the bit cells associated with other word lines are being read or written. Reading from a bit cell involves pre-charging the bit line signals for the corresponding bit cell position for all the word lines and discerning the logic levels when the passing gates are rendered conductive at a selected word line. Writing to a bit cell involves applying bit line voltages when the passing gates are conductive, to cause the cross coupled inverters to assume a desired logic state.
However the bit cells are subject to current leakage to a degree and along leakage paths that depend in part on the voltages at the bit cell nodes, and at the bit lines BL, BLB. Where a potential difference exists across the source/drain or gate/substrate of the transistors of the inverters or passing gates, some current leakage occurs. In a low power SRAM, it would be advantageous to reduce or eliminate current leakage. According to some techniques, the bit line voltages BL, BLB (which are isolated from the inverters by the passing gates) can be allowed to float when in a sleep mode and are precharged when switched into a ready or standby mode. But it will generally be the case that a potential difference exists between the bit cell nodes and the bit lines. The bit cell nodes are at complementary logic levels, one being at the cell positive supply voltage and the other being at the cell negative supply voltage. The bit cells at different word lines may have either logic state and are coupled to the same bit lines at each bit position. If all the bit cells at a given bit position happened to have the same logic level (the same data value), then minimum leakage might be obtained by floating the bit lines BL, BLB at the corresponding cell supply voltages. But the bit cells can have any arbitrary logic level. It would be advantageous if the bit lines could be controlled to float at levels that minimize leakage by adapting to the logic levels that happen to be stored in the bit cells.
Precharging of the bit lines, for example in preparation for a read operation, can be accomplished by applying a control voltage signal BLEQ, such as a VSS low voltage level, to the gates of two PMOS FETs that operate as pull-up switches. Each FET respectively couples one of the complementary bit lines BL, BLB to the positive supply VDD. The gate of a third PMOS FET can couple the bit lines BL, BLB to one another such that both bit lines are brought to equal voltages. When the read operation occurs, the imbalance in current to the opposite nodes of the cross coupled inverters is sensed to determine the bit cell logic state. Such sensing would be less dependable if the bit line voltages were unequal upon commencement of a read operation.
Isolating the nodes of the bit cell at the inputs/outputs of the cross coupled inverters, and also allowing the bit lines to float until a bit cell position is addressed, reduces but does not eliminate current leakage. Leakage paths remain, but depend on which of the cross coupled inverters is held in which of the two possible logic states. The leakage paths include FET drain/source leakage and gate leakage according to the different voltage bias conditions inherent in a logic state.
According to one technique for limiting power dissipation, an SRAM bit cell array can be partitioned into banks. Unused banks of bit cells can be maintained in a “sleep mode” until needed. The sleep mode can be associated with reduced potential difference across the bit cell power supply terminals, e.g., a reduced positive supply voltage VDD and/or an increased negative supply voltage VSS (nominally ground potential), so that leakage is reduced because the bit cells are subjected to reduced voltage bias that is minimally sufficient to maintain the bit cell logic values. When a bit cell or bank is to be switched from sleep mode into a standby mode and ready to be accessed for read or write operations, the bit cell power supply voltages must be restored to nominal levels. Floating bit lines BL, BLB must be precharged for read operations. These restoration steps when switching from the sleep mode to the ready or standby mode and preparing for a memory access operation, take time that can adversely affect the maximum operational speed. Restoration steps also consume power, and require that the power supply and its conductors have sufficiently high capacity and sufficiently low IR voltage drops, to handle the increased loading associated with switching into the standby-ready mode.
It would be advantageous to provide improved techniques for managing the voltages on bit lines BL, BLB when in the sleep and standby modes, to minimize current leakage, and to ease the load of switching into the standby mode for commencing a memory access operation.